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National Repository of Grey Literature 3 records found  Search took 0.01 seconds. 
Middle-level control of FB-MMC converter in Delta connection
 Kokeš, Petr
Control of a modular multilevel converter (MMC) is technically far more complicated than control of a standard 2-level converter. It is not only because of a great number of series-connected cells. For a MMC converter we need to cope with another control level (mentioned here as the middle-level control), which means balancing of voltages among MMC branches and the control of currents circulating inside this converter. For the Delta connected MMC with full H–bridge (FH) cells a convenient method for voltage balancing among all three MMC branches has been analysed and the appropriate control structure has been designed. Then the functionality of this balancing method has been verified using computer simulations and also tested with two MMC physical models operating as active power filters on 400V and 6kV grids.
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Lowest Level Control for FB-MMC Converter
 Kokeš, Petr
The analysis and comparison of two basic methods for the lowest level control of the Delta-connected FB-MMC converter (Full Bridge, Modular Multilevel Converter) have been performed. The first method is the SA-PWM modulation (Sampled Average PWM) with cell voltage balancing of SORT-BAL type, where cells are sorted according to their voltages. The other is the PSC-PWM modulation (Phase Shifted Carrier PWM) with FBCK-BAL balancing, which uses feedback P-control of cell capacitors voltages.
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Control and balancing of 7-level voltage converter with reduced capacitance of three flying capacitors
 Kokeš, Petr
A method of the control and voltage balancing of a converter using 4-7L topology is described. The 7-level VSI employs flying capacitors, 3 of which have substantially reduced capacitance. Conditions are explained under which the mentioned VSI can be controlled using the 4-level space vector modulation. Three algorithms of capacitor voltage balancing were developed which differ in complexity. All of them were verified by computer simulations. A simple basic variant has been realized in FPGA and tested in a LV 4-7L VSI model.
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